module rsff (
    clk, r, s, q
);
    parameter n = 1;

    input clk;
    input r;
    input s;
    output q;
    reg q = 0;

    always @(posedge clk)  begin
        if ( r & ~s )
            q = 0;
        else if ( s & ~r )
            q = 1;
    end
    
endmodule